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Introduction

Multi die packaging solutions, primarily 2.5D and 3D packaging, are being proposed for applications ranging from cell phones to high performance networking systems. The motives for these approaches vary from cost reduction and form factor miniaturization to power reduction and performance enhancement. A host of alternate approaches to 2.5D and 3D silicon are emerging due to cost and supply chain concerns. The symposium will identify strategies and enabling technologies for Multi Die Integration and explore emerging alternate approaches. A panel session will identify the drivers that require OEM’s to consider multi die packaging. A major hurdle to the adoption of multi die Integration – Known Good Die (KGD) and multi die testing – will be addressed the following day in a symposium at the same location.

Session 1: Multi Die Integration Strategies
Session Chair: Patrick Tang, STATSChipPAC

Tablet, smartphone, handheld, portable, and wireless products continue to be driven by the need for reduction in size and weight while at the same time meeting the demand for increased functionality, high density, speed, and performance. Component integration plays a key role in meeting these needs and demands. Multi-die integration, the combining of multiple components in a single package or on a single substrate, provides an effective solution for advanced integration. These multi-die integrations are not constrained by common wafer fabrication processes and can integrate passive components to create self-contained systems. The key attributes of multi-die integration strategies will reviewed, die interconnect technology selection issues and methods for assuring product quality will be addressed and what the multi-die integration landscape will look in 2013 and beyond.

Presentations to include:

Multi-Die Integration Strategies and System Partitions in Mobile WWAN Devices
Dr. Hsin-Chin Chang, Vice President, Universal Scientific Industries, Co., Inc.

The hardware design of the smart phone has been evolving toward the trend of miniaturization aggressively in recent years. Tear down examples from various successful designs were given in the presentation. Nevertheless, the industry continues the drive for further miniaturization in order to allow for thinner and lighter design, as well as for more spaces for battery, antenna, and acoustic. In order to facilitate further miniaturization, utilizing of the electromagnetic design and simulation is essential.

The technical rationale is two-fold. One is that the clock speed of the application processor already exceeded 1GHz, and will exceed 2GHz and further. Hence the design of the high speed digital circuitry involves in-depth understanding of the RF characteristics. The other is that the complexity of the multi-mode and multi-band RF front end design of the 3G to 4G modem calls for the considerations of the couplings and parasitic capacitance/inductance derived from the very compact structure.

Examples of such SiP “System in Package” design were given in the presentations, including complete single SiP 2.5G data modem, and multi-band 3G + LTE RF frond-end modules. The process to design, simulate, and measure these SiPs are explained and discussed.

Multi Die Integration: A Case Study
Y.S. Kim, VP of  Engineering & R&D, Signetics

Case studies of Memory Multi Chip Packaging and eMMC (embedded Multi Media Card) will be discussed based on high volume manufacturing experience. Both MCP and eMMC are widely used for SmartPhones as a storage solution. MCP is the package level integration of heterogeneous memory chips, and eMMC is the further integration of NAND with Flash Card Controller and passives. The yield of Multi Chip packaging becomes a critical consideration, since the affected lot size at the assembly step becomes 2 to 5x larger than single chip package if the yield is found to be low at final test.

The back grinding condition of NAND flash, Die Attach Film and its cure condition, filler damage during the mold process are identified as critical steps. Also, DC test yield feedback at the assembly site becomes an effective tool to closely monitor the yield.

Alternatives on the Road to 3D TSV
E. Jan Vardaman, TechSearch International, Inc.

The demand for 3D TSV technology remains driven by performance such as high bandwidth between memory and processor and the need for lower power. While the drivers for 3D TSV remain constant but the time line for its adoption keeps shifting out. Several technical challenges and business logistics and infrastructure issues are delaying the full commercialization of 3D TSV. These issues include, design, the debonding step in wafer thinning, thermal dissipation, and test. Several companies are developing new materials that may improve yield and, improvements in equipment are expected in the future. EDA tool improvements to enable thermally aware designs are anticipated. The introduction of 3D TSV will also require new developments in test methodologies. Known good die is a requirement in order to provide sufficiently high yield to makes the process cost effective. Companies are still discussing issues such as whether to probe or not to probe wafers, the use of BIST, and required test methodologies. Supply chain issues are still under discussion.

While these issues are being resolved, companies will use alternative such as package-on-package (PoP) with fan-out WLP or embedded die in the bottom package, stacked die with wire bond, and interposers (also called 2.5D). This presentation describes various applications and the planned alternatives.

Session 2: Enabling Multi Die Integration
Session Leader: Kumar Nagarajan, Maxim Integrated

Multi die integration using 2.5D/3D IC is becoming the natural evolution of semiconductor technology since it enables integration of heterogeneous functionality and process technologies, complementing “Moore’s Law” transistor scaling for different end market applications. It offers unique benefits such as increased capacity, improved performance, reduced power consumption, reduced footprints, faster time-to-market and lowered risk/cost.

Various facets of the semiconductor industry such as Process/Package technology, Equipment technology, Material technology, EDA tools, Standards, Test, Metrology, Characterization, Reliability, FA have to come together to enable the transition into 2.5/3D IC. This session will discuss the enabling technologies and key trends that make multi die integration possible.

Presentations to include:

Silicon Interposer Design: Architecture through Implementation
Bill Acito, Product Engineer, Cadence

The buzz in the semiconductor industry over 3D-ICs and 2.5D integration continues to escalate. Today, many designs are implementing through-silicon-vias (TSVs) in passive silicon rather than active silicon; dies are being integrated side-by-side on a silicon-based substrate (interposer) and connected through silicon-process local interconnect.

While much of the discussion involving silicon interposers has been related to manufacturing, some are thinking broader and looking at the silicon interposer as a part of an overall system. This requires consideration of a silicon substrate as part of an integrated chip-interposer-package-PCB environment. There is great value in early system planning that includes the interposer so that cost of the system can be reduced and electrical performance maximized.

The Strange World of Networking Memory
David Chapman, VP Marketing & Applications Engineering,
GSI Technology

The development of memory devices for the computer market continue to rely on increasing date bandwidth to improve performance...but the networking market has always needed something else...high transaction rate. As we move forward into a new age of fine pitch interconnect, the fundamental differences in the performance requirements of different markets will continue to drive demand for performance differentiated memory devices. In this presentation GSI will describe what makes networking different and describe what GSI is doing to drive a networking memory roadmap that will carry the industry into the next decade.

Multi Die Integration – Can Material Suppliers
Meet the Challenge?
Jeff Calvert, Global R&D Director, Advanced Packaging Technologies (APT), Dow Electronic Materials

A conundrum for materials suppliers relative to multi die integration is that with so many technical issues to address how can one be sure a material addresses the most important technical hurdle and know it is the right one? And, with so many players in the game setting different rules, how does one determine which design scheme will take hold? With so many applications and many potential integration options, it can be quite intimidating for material suppliers. Achieving economies of scale to meet cost targets is an enormous concern and there isn’t a material supplier out there that doesn’t want to take the gambling aspect out of the decision making. To manage this risk, one approach suppliers can take is to develop material platforms that are customizable and address common demands and requirements whenever possible. In the end, cost/performance trade-offs will be the determining factor for adoption of a material and it pays to embrace this certainty. This presentation will address the issues, challenges and potential solutions to enable packaging engineers with right packaging material solutions for variety of needs in multi die integration.

Session 3: Emerging Technologies for Multi Die Packaging
Session Chair: John Xie, Altera

Multi-die packaging technology carries a new meaning today, with much increased system bandwidth requirements and fast progress in advanced interconnect technology and its integration with latest generation of silicon technology.  It also fills the gap between high density and high cost 2.5D/3D integration solution and traditional 2D packaging solution. This session will include discussions covering advanced substrate technology, high density MCP assembly technology, design and performance consideration, possible business applications etc.

Presentations to include:

The Changing Face of Organic Substrate Technology
in 3D Era

Chaowen Chung Ph.D., Marketing Director,
Unimicron Technology Corp.

Due to the market demand, more functions and processing power are put into electronic packaging systemS. Also reducing the over packaging and module dimensions becomes a continued effort in the electronic industry. Traditionally the most popular substrate is made of organic materials reinforced by glass fiber. However, due to requirement above, the substrate technology becomes more versatile. There are several organic substrate technologies are emerging that will be discussed.

• Low CTE substrate materials with CTE close to that of silicon.

• Substrate materials with a lower dielectric constant and dispassion factor for high frequency applications.

• Embedded technology, both embedded active and passive components into the substrate.

• Use thin core and even coreless technology for a better electrical performance with thin profile.

• Fine pillar substrate technology to support PoP structure.

• Organic interposer technology that requires 5/5 or even 3/3 um fine line patterns in the organic substrate.

Organic Interposers
Joseph Dang, Field Applications Engineer, Kyocera America, Inc.

Kyocera has developed an advanced build-up substrate technology with a composite CTE of 10-13 ppm/C. This low CTE organic material reduces the thermal mismatch between chip and substrate that enables tighter flip chip pitches down to as low as 120um.

The technology is called APX (Advanced-SLC™Package X), which consists of core and build-up materials with copper circuitry. The new build-up film maintains both conductivity and dielectricity with 10/10um line/space and 25um via diameter. The core material has excellent reliability properties with 57um through-hole diameter and 120um through-hole pitch.

Substrates with these newly advanced design rules and material properties can enable smaller chip sizes, and lower thermal stress during the flip chip assembly. This presentation will discuss the key features and potential applications.

Low Cost Interposer Solutions for 2.5D Packaging
Young Do Kweon, Vice President, Samsung Electro-Mechanics
Co., Ltd.

In order to achieve high density and high performance package, three dimensional chip integration has been desired. 3D chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. There are many approaches to 3D packaging. 3D ICs designed with TSV offers the ultimate in 3D integration, but currently it can be only adopted to high-end products because of cost issues such as known good die (KGD), expensive process cost, etc. 2.5D interposer stacking could offer alternate solutions. However, silicon interposers still have cost issues. If organic technology can replace silicon technology, it could be an innovative packaging solution.

Multi Die Integration for High Bandwidth
Networking Devices … a User Perspective

Ray Niu, Sr. Component Engineer, US R&D Center, Huawei Technologies

The demand on bandwidth for high end networking and computing applications escalates as high as ten times for every new generation of silicon, which results into serious challenges for the processor and memory device. The gap between system requirements and current memory technology is increasing at an alarming rate. Developing new solutions which can adequately respond to these needs, while concurrently mitigating the reliability, cost and manufacturability risks is becoming critical. 2.5D/3D IC integration with high density connection, high bandwidth and low power consumption appears to be a very promising solution. However there are serious hurdles to overcome first including thermal, test, cost and reliability before this becomes a reality.

Session 4: Panel -- Drivers for Multi-Die Packaging
Session Chairs: Ivor Barber, LSI and Rich Rice, ASE (US) Inc.

During this symposium the speakers will explore multi die integration strategies, enabling technologies related to packaging and its infrastructure, as well as emerging technologies and approaches. In a panel session these speakers and other industry experts will interact with attendees to discuss and explore the new opportunities, barriers, and future work needed for packaging solutions in the era of 2.5D and 3D multi die integration.

Panelists

• Joseph Dang, Kyocera
• Dave Love, GenapSys
• Steve Smith, Synopsys
• Alex Tsai, TSMC North America
• Jan Vardaman, TechSearch International

Ivor Barber, Director, Package Design and Characterization,
LSI Corporation – Symposium Chair

Rich Rice, Senior Vice President of Sales, North America,
ASE (U.S.) Inc.

Discounts are offered for both this event and the Known Good Die conference. Exhibit spaces are limited. Exhibit fee includes:

6’ table, draped
2 chairs
11”x17” custom table top sign with your logo & company description
One admission to the conference
Logo on event home page
Logo, link to your URL and company description on special
Exhibitor web page
Company description in the symposium proceedings
Printed and electronics versions of the symposium proceedings
Marketing exposure through e-mail campaign

Click here for pricing and to reserve a table. For more information contact Bette Cooper at bcooper@meptec.org or call 650-714-1570.

Sponsoring this event will provide a valuable opportunity to promote your company brand and product/service message to attendees, while supporting your business development and positioning goals. For pricing and benefits click on the Application Form link below. Discounts are offered for Sponsorship opportunities for both this event and the Known Good Die conference. For more information contact Bette Cooper at bcooper@meptec.org or call 650-714-1570.

Sponsorships available:

One – Diamond SOLD OUT
Two – Platinum
Three – Gold
Unlimited – Silver
One – Lanyard SOLD OUT

Cost of admission includes attendance, continental breakfast, refreshment breaks, lunch, and printed proceedings. A credit card is needed to hold the reservation.

Pre-registration is strongly recommended. There will be no guarantee of space or materials for on-site registrants.

Final confirmation including maps and directions will be sent by November 9.

Refunds for advance payment, less a $50 processing fee, will be given in full provided cancellation by phone or e-mail is received 10 business days before the event (Wednesday, October 31). If you do not cancel by October 31 or are a no-show, the credit card provided to hold the reservation will be charged for the full amount.

MEPTEC has secured a special rate at the Biltmore Hotel of $129.00. Call 408-988-8411 or 800-255-9925 to reserve your room. Be sure to mention MEPTEC in order to secure your special rate.

There are very few technologies that are truly seminal and game changing; 2.5D appears to be one of them. There is a confluence of events that make this technology compelling. The inexorable demand in the market for escalating bandwidth is so potent that the present memory technologies cannot keep up with it. Wide I/O memories are fast becoming indispensable and their application is becoming feasible with powerful enablers like 2.5D technology. The integration of ASIC and memory, and other heterogeneous chipsets on a Silicon interposer, allow many benefits including miniaturization and enhanced performance. Next generation node scaling, our favorite pathway to keep up with Moore’s law is becoming exorbitantly expensive. The technology landscape of the future will have fewer advanced semiconductor fabs, more companies going fabless and more companies leveraging opportunities offered by 2.5D packaging. Before we can materialize the promises of 2.5 D technology there are significant hurdles and pitfalls the industry will have to overcome. Pre-competitive collaboration would be a very prudent approach to bring us all closer to the vision much faster.

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