©2018 MEPCOM LLC/MEPTEC
SESSION 1: Market Drivers and Supply Chain Collaboration
Session Leader: Dan Tracy, D.P. Tracy Associates
Heterogeneous Integration will deliver increase system functionality in a small footprint, and to achieve such solutions will require collaboration along the electronic industry’s supply chain to solve and address the challenges. This session will provide a perspective of the challenges for supply chain participants in terms of collaboration; highlight market drivers and the opportunities for collaboration; and identify how business models will adapt, change, and evolve to deliver solutions needed to achieve Heterogeneous Integration. Effective collaboration, aligned with the market needs, will enable our industry to deliver cost-effective and reliable solutions for Heterogeneous Integration.
Keynote Speaker:
Heterogeneous Integration: Is it Ready for Changing the Packaging Landscape?
Risto Puhakka, President, VLSI
IC manufacturing will change as the node transitions slow and classic shrinking becomes more difficult and expensive. Heterogeneous Integration is often claimed to be the cure for these challenges. However, is it ready for the prime time?
The presentation takes a long view on the packaging interconnect technologies and explores under what conditions Heterogeneous Integration is able to create substantial change in the IC packaging landscape. This is a prerequisite to achieve reasonable market share among interconnect technologies and creating fundamental change in the IC packaging business.
Cost Effective Solutions for System Integration
Dr. Dongkai Shangguan, Vice President for Advanced Manufacturing Engineering, Flex
This presentation will review the SiP technology landscape, discuss various solutions and competency requirements, as well as supply chain challenges, for miniaturized modules for system integration across market segments.
Why Heterogenous Integration? The Answer is Economics!
E. Jan Vardaman, President, TechSearch International, Inc.
For years, as companies moved to new logic designs more and more functionality was integrated into the chip and system-on-chip was the rule of the day. Gordon Moore observed that the number of transistors in a dense integrated circuit doubled about every two years and correspondingly, the cost decreases. It was an observation about economics.
With the cost of lithography increasing dramatically, moving to the next semiconductor node becomes very expensive, especially if the idea is to fabricate a very large chip, not to mention the design cost.
The idea of heterogeneous integration is to only design what is absolutely necessary in the most advanced semiconductor node and then use that chip in combination with others in a package that provides the desired function in a more cost effective manner. IP reuse can also reduce cost. Heterogeneous integration also allows functions that could not be fabricated on the same die to be placed in a package together. There are many package solutions that can achieve this goal. This presentation discusses many of these solutions ranging from high performance to consumer.
SESSION 2: Design and Test of Chiplets and Multi-die ICs
Session Leader: Herb Reiter, eda 2 asic Consulting, Inc.
Integrating heterogeneous functions - as "Chiplets" - into advanced IC packages offers lots of flexibility, saves space and increases performance per Watt. However, multi-die ICs demand closer cooperation and more bi-directional data to flow across the supply chain, to get to revenue faster, reduce unit cost and risk.
In this session experts from across the multi-die EcoSystem will outline common challenges as well as explain proven solutions and ongoing enhancement efforts. In addition, executives from the Electronic System Design Alliance (representing EDA, IC and system design firms) and from SEMI (representing IC manufacturing & test companies and their suppliers) will outline why they recently formed a Strategic Alliance and describe how they'll contribute to significantly closer cooperation across the entire supply chain.
Keynote Speaker:
Disruption is Coming: Adapt, Change or Be Left Behind
Keith Felton, Product Marketing – IC Packaging, Mentor Graphics Board Systems Division
New, emerging and existing markets demand ever-smaller electronic devices that surpass the performance of their physically larger predecessors with thinner and smaller form factors, lighter, increased functionality with faster data transfer, and without sacrificing battery lifetime and affordability. Enter a new breed of packaging that we term as High Density Advanced Packaging (HDAP) it’s the evolutionary offspring of its silicon foundry and organic package OSAT parents, where genes of both are mixed and result in something that can be highly disruptive. These next generation packages can come in different forms, the most well-known is FOWLP, that itself has multiple flavors, InFO from TSMC which was made famous by Apple, SWIFT from Amkor, M-series from DECA and there are others. Even within FOWLP there are many varieties. Of course there are other new integration platforms such as silicon interposers, sometimes call 2.5D which can be mixed with FOWLP or with an organic BGA package or even both. Implementing this new generation of packages requires a significant expansion in the communication between the IC design world the package design world plus a new dimension, that of communication and interaction with the OSAT/Foundry that will fabricate and assemble the complete device. This presentation will explore best practice approaches for embarking into HDAP design, how to leverage your Foundry or Outsourced Substrate Assembly and Test (OSAT) partner, how to ensure your design is manufacturable first time, avoiding expensive and time consuming changes or redesign.
Design and Manufacturing – From Silos to Strategic Collaboration
Bob Smith, Executive Director, ESD Alliance (a SEMI Strategic Association Partner)
Bettina Weiss, Vice President Business Development, SEMI
Applications for semiconductor technology have moved from monolithic (computing, mobile and networking/communications) to wide ranging (IOT, autonomous driving, AI) devices, bringing with them innovative new applications that were virtually unknown just 5 years ago. At the same time, the semiconductor and adjacent industries have experienced unprecedented consolidation, significantly changing supply chain dynamics and opening the door for new, often big, players. This presentation addresses, from the vantage point of a global industry association, how not-for-profit, member-driven organizations need to partner smartly and provide their members opportunities to connect, collaborate and innovate together. The presentation will focus particularly on the integration of the ESD Alliance as a SEMI Strategic Association Partner and the opportunities that their members can now realize when connecting the vibrant electronic system design and IP community with global platforms – where 1+1 >2.
As the Industry Starts to Look Away from SOC and Towards Heterogeneous Integration, What New Challenges are Emerging for Design and Test?
John Park, Product Management Director, IC Packaging and Cross-Platform Solutions, Cadence Design Systems
Lisa Jensen, Product Engineering Director, Modus DFT Software Solutions, Cadence Design Systems
Gordon Moore predicted a trajectory in which the transistor count of IC’s would double every two years driving transistor cost on a constant downward path. This prediction later came to be known as Moore’s Law. For the past several decades, the electronics industry has thrived while enjoying the benefits of Moore’s Law. It’s been a great run. However, the new semiconductor growth engines like HPC and AI are forcing engineers to consider design alternatives to SOC. In many cases, they are looking at advanced, multi-chip(let)/system in a package (heterogeneous integration) technologies to not only solve the next generation of design challenges, but also keep costs in check. This presentation will provide an overview of the latest trends in heterogeneous integration and describe some of the design/test challenges that will need to be addressed to support the next generation of multi-chip(let) designs.
SESSION 3: The Manufacturing Challenges of Heterogeneous Packaging
Session Leader: Joel Camarda, Altierre
The complex heterogeneous SIP (system in package) may contain a mix of interconnection technologies and materials. The interconnect may be wire bonding (gold, copper, aluminum) , flip chip (solder bump, copper pillar, micropillar), TSV, sputtered meatal, fusion bonding, and/or combinations thereof in the same package. Wafer fab manufacturing technologies have migrated into the package. Substrates and interposers may include lead frames, patterned silicon, glass, or organic. Die stacking is becoming widespread, performed at wafer level or single chip to single chip. This manufacturing session will feature technical experts from prominent equipment and material suppliers and OSATs discussing their leading edge capabilities currently in production and their assessment of their next challenges.
Keynote Speaker:
Heterogeneous Integration Roadmap – Driving Force and Enabling Technologies for Systems of the Future
Rich Rice, Senior Vice President of Sales, ASE (U.S.) Inc.
The electronics industry has reinvented itself through multiple disruptive changes in markets, businesses, and technologies. We are now entering a new era of disruptive changes in market, industry and technology. With the expanding digital economy, we are seeing data migration to the cloud, smart devices everywhere, Internet of Things expanding to the Internet of Everything, and the emergence of autonomous vehicles. While Moore’s Law is slowing, electronic and semiconductor innovation continues to accelerate at unprecedented pace.
Heterogeneous Integration through SiP for multi-chip devices is moving into the mainstream, driven by requirements in functionality, cost effectiveness and time-to-market. System integration is a major focal point, with complex tradeoffs including size, weight, latency, power requirement, thermal management, bandwidth density and cost. It is clear that progression of innovation will rely on visibility and understanding of what lies ahead. The crucial question is, what are the critical paths going forward?
The cognizance of this crucial question inspired the creation of the Heterogeneous Integration Roadmap, a mechanism established in 2015 to identify difficult challenges, potential solutions and viable opportunities for pre-competitive collaboration in this new ecosystem of heterogeneous integration. Following ITRS, the Roadmap will look 15 years out to the future, and 25 years for emerging devices and emerging materials. The Roadmap is sponsored by three IEEE Societies (EPS, EDS, & Photonics) together with SEMI & ASME EPPD. With the first edition of the Heterogeneous Integration Roadmap due to be released by the end of 2018, Rich Rice, co-chair of the HIR automotive working group, will present an overview of the roadmap &and the progress being made in building an informed and cohesive heterogeneous integration roadmap ecosystem.
Advancements in Assembly Equipment for Heterogeneous Integration
Horst Clauberg, Director of Advanced Packaging Process Engineering, Kulicke & Soffa Industries, Inc.
There is a clear market growth for packages requiring heterogeneous integration with new packages being developed at a prodigious rate. These new packages require the use of enhanced and novel packaging technologies and provide R&D opportunities for assembly equipment manufacturers. Some of the new assembly requirements are bonding large die or die with ultra-high density interconnects, placing with high accuracies, bonding new interconnect material sets, assembling packages with a combination of bare die, packaged die, and passives efficiently. All of these need to be accomplished with high productivity and cost effectively.
Building Blocks of Heterogeneous SoCs
Chris Scanlan, Sr. Vice President of Development, Deca Technologies
As the electronics industry embraces the power of heterogeneous integration, critical new building blocks are required to realize the potential breakthroughs in performance, size and cost. Abandoning the monolithic silicon substrate of classic SoCs brings the fundamental challenge of fab BEOL-level electronic interconnect across multiple independent semiconductor devices. Adaptive Patterning uniquely aligns every device contact with the interconnect fabric while a planarized structure enables scaling to sub-micron features.
SESSION 4: Panel Discussion: Supply Chain Issues for Advanced Packaging
Moderator: Ed Sperling, founder and Editor-in-Chief, Semiconductor Engineering Magazine
The slowdown in Moore's Law has forced companies to rethink architectures and IP and how to integrate everything together, but realigning the supply chain around a long list of packaging options is a huge undertaking. It requires a secure marketplace, varying levels of characterization, and support from foundries and OSATs. And it requires the industry to commit to standards and processes that so far don't exist in order to maximize yield and reduce unexpected interactions, potential security issues and improved performance with lower power at a reasonable cost.
Panelists:
Chenglin Liu
Director, Packaging Engineering, Marvell
Juan Rey
Vice president of Engineering, Calibre, Mentor
Rich Rice
Senior Vice President of Sales for ASE (U.S.)
Eric Tosaya
Senior Director Package Manufacturing, eSilicon