SPEAKERS & ABSTRACTS

Speakers confirmed as of 11/3/15
Speakers listed alphabetically within session

Tuesday, November 10, 2015

The Genius of Cars – and why Semiconductors Matter

Challenges and Solutions in Automotive IC Assembly
Prasad Dhond, Senior Director, Quad and Dual Leadframe Products, Amkor Technology

Automotive electronic systems represent some of the harshest application conditions for integrated circuits (ICs). The packaging for these ICs must withstand a variety of tests that go well beyond conditions prevalent in consumer, commercial and even industrial qualifications. To survive these tests and operate properly over their expected lifetime in a variety of vehicles and systems, assembly processes for automotive ICs have several unique aspects to ensure packaging reliability and durability. This presentation will explain several key factors that must be considered when assembling an automotive IC.

System Scaling, A New Fundamental Electronics Frontier Technology for Smartphones, Automotive Electronics and Other Heterogenous Electronics Systems
Rao R. Tummala, Joseph. M. Pettit Chair Professor and Director, 3D Systems Packaging Research Center, Georgia Institute of Technology

This presentation will highlight the need for a new fundamental system scaling technology. Semiconductor and systems landscape is changing dramatically. ICs, on one hand, for the most part, are becoming commodities, providing much lower profit margins than ever before, leading to industry consolidation to less than five companies within the next decade, worldwide. In addition, the cost and complexity of transistor scaling is growing exponentially. There is no longer a cost reduction as the next node is introduced with higher transistor density. The driving engines for electronic systems, on the other hand, are also changing dramatically to smart, wearable, wireless healthcare and wireless networks, requiring an entirely different vision and strategy than transistor scaling alone that was practiced during the last 60 years. These systems are small to ultra-small systems and yet must perform dozens of functions that include Wireless, Health-Care, Wearable, MEMS and Sensors, Camera, mm-wave, Digital, Photonics, Analog, Power, and many others, all in a thickness of no more than 6000 microns at a cost that every consumer could afford.

Others to be announced

High Speed Components and Packaging

Narrowing the Gap between Packaging and System
Ou Li, Director of Engineering, System Group, ASE (US) Inc.

With fast growing of today’s electronic world, system integration is realized through multiple aspects. Advanced packaging technologies and system in module and package are proliferating. Furthermore, early design stage collaboration among chip, package and system are also critical. Chip-Packaging-System co-design is becoming a more imminent for performance, form factor, cost and time to market. This presentation talks about advanced packaging solutions for system integration, and how Chip-packaging-system co-design is enabling the “Virtual IDM” in electronic ecosystem. The presentation will also cover typical co-design tool box, development flow and few case studies. The ultimate goal is to narrowing the gap among chip, packaging and system level through partnership and collaboration.

Package Technology and Design Enablement to 56Gbps Transceivers
Hong Shi, PhD, Director, Package Design, Xilin

The demand to 400G/1TB data path requires ultrahigh speed transceiver operating at 56Gbps for low power and economical system implementation. While system architects continue debating whether 56G NRZ or 56G PAM-4 should prevail, the package and interconnect designers would need to prepare well for either or both to come into implementation. Because 56G NRZ and 56G PAM-4 carries distinctly unique characteristics, the challenge to package development is different.

This talk will cover recent studies performed in understanding unique requirements from 56G NRZ and PAM-4 to next generation packages. The package development is addressed from both enabling substrate technology and design solution in meeting greater than 30GHz bandwidth and as low as -70dB lane-to-lane cross-coupling. All has to be achieved at same or lower cost than the 28Gbps generation.

High Speed ASIC Packaging Trend: Integration, SKU, and 25G
Larry Zu, Founder and President, Sarcina Technology LLC

Today, high speed ASIC packaging has replaced microprocessor packaging as the driver for high performance semiconductor package design, simulation, substrate manufacturing and assembly. In this area, multi-die integration has been used for many years. The concerns about module yield and the technical challenge of warpage-induced PCB assembly yield loss for large packages have been resolved. After the multi-die single package’s wide adoption, the single-die multi-package approach has started to gain traction. Due to increased package cost, demand for small packages that fit into a small network card, high tape out costs for new chips and the time to market requirement, more and more companies today design an ASIC die with multiple packages. This approach offers minimum cost and most importantly, provides the shortest time to market. Finally, package design for 25G+ SerDes has become a popular topic. The wild differential impedance variation caused by BGA ball and other vertical interconnections creates reflection and degrades eye height. Traditional design tricks effective for 10G SerDes no longer work at the data rates for 25G+ SerDes.

Medical and Wearables for Human Health: Connecting the Dots from Silicon through Packaging

Integrated Circuit Design for Miniature Implantable Medical Devices
Andrew Kelly, IC/Systems Architect, Cactus Semiconductor Inc.

A new generation of Miniature Implantable Medical Devices (MIMDs) has arrived. Thanks to advances in micro-electro-mechanical systems (MEMS), electronics packaging, and battery technologies, coupled with some creative integrated circuit (IC) design, these new devices are a fraction of the size of traditional Implantable Medical Devices (IMDs). The new MIMDs can be implanted at the point of therapy or sensing, thus eliminating the need for long leads, and enabling minimally invasive surgical procedures. To maximize the benefits of various new technologies, the electronic circuits in MIMDs must be designed specifically to their unique characteristics and requirements. This presentation describes design approaches that help to capitalize on the available opportunities, and enable the dramatic miniaturization required for the new generation of MIMDs.

Miniaturization of Cochlear Implants
Kurt Koester, Director of Implant Technologies, Advanced Bionics

This talk will cover the trend towards the miniaturization of medical devices by reviewing the history and experience in the cochlear implant field and discuss some of the challenges that size reduction imposes on the design of active implantable devices. To successfully achieve miniaturization targets, it is generally necessary to simultaneously decrease the size of hermetic packaging and the electronics and component payload inside the device. Other aspects of the cochlear implant application, e.g., head-level device placement, designing systems with implantable and body worn components, and covering the pediatric and adult use-cases make device miniaturization desirable. However, these issues drive different designs considerations, test requirements, device characterization, and longevity expectations relative to other active implantable devices and these issues will also be discussed.

Sensors, Power Management and Energy Harvesting

22FDX technology enables energy harvesting solutions
Jamie Schaeffer, Ph.D., FDSOI Product Line Manager, GLOBALFOUNDRIES

22FDX technology is a novel semiconductor technology with features including software controlled body-biasing, ultra-low power operation, and integrated RF that when used in conjunction with energy harvesting can help to reduce service costs and extend the operational life of IoT edge nodes. This talk will review the compute, power, connectivity, storage, and low cost needs of pervasive and intelligent IoT applications. IoT edge nodes that are remotely located or inaccessible will utilize energy harvesting techniques placing further demands on the power management, serviceability, and reliability requirements. This talk will discuss how 22FDX is uniquely positioned to address these challenges with the ability to minimize active (0.4v operation) and standby (~1pA/um) power consumption, provide low-power RF connectivity, and deliver dynamic configurability of the transistor in reaction to the environmental conditions of the energy harvesting system.

Gallium Nitride: A New Multifunctional Sensing Platform
Prof. Debbie G. Senesky, EXtreme Environment Microsystems Laboratory (XLab),
Stanford University

AlGaN/GaN high electron mobility transistors (HEMTs) are being exploited in the design of high-frequency power electronic devices. The two-dimensional electron gas (2DEG) at the interface of this unique heterostructure can also be leveraged for the development of multifunctional sensing technology as GaN is simultaneously piezoelectric, piezoresistive and pyroelectric. It is envisioned that a multitude of devices such as inertial sensors, chemical sensors, bolometers, micromechanical resonators and energy harvesters can be microfabricated in a monolithic fashion with this material platform. However, the technological challenges (e.g., packaging, catalyst integration and temperature compensation) of this aggressive integration approach have yet to be mitigated: leaving room for intense research activities and product development. Also, the temperature-tolerance, radiation-hardness and biocompatibility of this material set can be used to extend the operation regime of micro- and nano-scale devices to extreme harsh environments (e.g., deep space, subsurface environments, combustion environments, and the human body). In this talk, a review of the advancements in microfabrication technology for GaN-based devices will be presented. In addition, the compelling results of GaN device operation at temperatures as high as 600oC and in high-radiation environments will be reviewed. The talk will close a future vision for GaN-based sensors and electronics.

Energy harvesting technology based on next-generation thermoelectric devices
Douglas Tham, Co-Founder & CTO, Silicium Energy

Energy harvesting technology based on next-generation thermoelectric devices is now coming to the commercial market, offering unprecedented performance advantages designed to revolutionize wearables and the IoT. The silicon-based thermoelectric devices developed by Silicium leverage heat emanating from the body or from infrastructure to create electrical power, via the thermoelectric effect, to drive wearable devices and industrial sensors. This presentation describes the Silicium technology itself, the story of how it was created at Caltech and at the University of Michigan, and details how Silicium’s silicon-based thermoelectric devices are manufactured, utilizing a "fab-less" approach using off-the-shelf silicon wafers.

 

Wednesday, November 11, 2015

Multi Die Integration

Silicon Interposers for Multi Die Integration
Ivor Barber, Senior Director of Package Technology Development, Xilinx, Inc.

Motives for adopting silicon interposer technologies include Performance Gain, Miniaturization, Integration of Disparate Silicon Technologies and Cost Reduction.

Xilinx introduced SSIT (Stacked Silicon Interposer Technology) with TSV (Through Silicon Vias) to reduce the cost of creating high end FPGA’s for applications such as next-generation wired communications, high-performance computing, medical image processing, and ASIC prototyping/emulation.

This presentation will show how SSIT reduced high end FPGA product cost and how recent advances are allowing even larger devices to be created. Lastly the presenter will discuss integration and cost reduction strategies to address emerging opportunities in IOT and Edge Computing (distributed computing at the edge of the Network) to facilitate multi die integration in relatively low cost environments such as autonomous vehicles, automated factories and  smart homes.

Challenges in the Development of Cost Effective Multi Die Integration Solutions
Vincent Liao, Technical Director, ASE

System-in-Package (SiP) modules play an important role to make portable and wearable devices thinner and smaller, to integrate more functions, and to reduce time to market. For multi-die SiP module designs, package level EMI shielding, Antenna on Package (AoP), Double Sided molding, and embedded die substrates have been proposed and developed by Advanced Semiconductor Engineering (ASE), Inc. to be implemented for complex but cost effective, miniaturized solutions. This presentation will discuss the challenges for development and implementation of these technologies in high volume applications.

The Development of Cost Effective Multi Die Integration Solutions for Emerging Connectivity (IoT) Emerging Applications
Trevor Yancy, Senior Analyst, TechSearch International, Inc.

Growing demand for connected devices and systems (commonly referred to as The Internet of Things (IoT) or the Internet of Everything) and the increased deployment of smart devices to collect data, transmit and/or process information is driving new requirements for semiconductor packaging. This translates into an increasing number of MEMS and sensors, processors, and RF devices. This presentation examines trends in multi die integration that are considered cost effective for the growing connectivity requirements. Formats include a variety of packages such as leadframe, laminate substrates, fan-out wafer level packages, and other alternatives. Many of these packages fall into the category of system-in-package (SiP).

On the Road to SiP and Modules

SiP from a Systems Perspective
Ilyas Mohammed, Sr. Director, Product Design and Development, Jawbone

Abstract to come

SiP and Heterogeneous Integration: An IC Manufacturer’s Perspective
Mike DeLaus, Manager, Wafer-Level Package Development Group, Analog Devices

The Internet of Things (IoT) era is driving profound changes in the semiconductor industry. IC manufactures, like Analog Devices, have had to adapt to these changes both in terms of the products they offer and the technologies that they employ. The increased emphasis on integration coupled with the limitations of device scaling are driving the need for packaging solutions like System in Package (SiP) and innovative heterogeneous integration schemes. This presentation will discuss how Analog Devices is meeting these challenges and providing their customers with more integrated solutions. The product development process will be described and the increased importance of collaboration, simulation and enhanced testing will be highlighted. Examples of ADI’s next generation devices, which seek to grab more of the signal chain, will be discussed.

Co-Design for High Density SiP Module: OSAT Point of View
Dr. Harrison Chang, VP Miniaturized Product Corp R&D, ASE

New generation of consumer electronics for smartphone and beyond smartphone (i.e. IoT, Wearable, and 5G) calls for high density integration of heterogeneous SiP module. For high density SiP Module, the component counts could be in the ranges of hundreds, and is being delivered in the semi-conductor industry. This new level of integration requires closer working relationship between IC House and OSAT than the industry is usually practicing. Among them, design for miniaturized manufacturing, leveled test development approaches, and structured failure analysis are crucial for the high density SiP Module projects to achieve low cost and time to market. In this presentation, several generations of manufacturing processes and structures of such high density, heterogeneous SiP Module are introduced, and the new working relationship will be illustrated.

IC-Package-System Co-Development in the New SIP Era

Product Co-development in the New SiP Era
Hui Liu, Senior Manager, Design Engineering, Altera Corporation

As silicon node scaling faces more and bigger challenges, such as power and SI/PI issues, reliability and yield issues, cost and IP integration issues, SiP solution becomes more and more attractive over single chip SoC. At the same time, SiP solution faces new challenges as well due to design and manufacturing complexity. To address these challenges effectively, this presentation introduces a new front-end co-development concept vs. the traditional backend co-design approach.

This presentation focuses on component level SiP solution co-development by IC and Packaging Engineering and Marketing. Specifically the presentation will cover:

• A multi-dimensional view (IC integration, packaging integration, co-development, and
• application) of the IC industry evolution
• SiP challenges in the new era
• Front-end co-development vs. backend co-design
• Front-end co-development attributes and methodology flow

The presentation will also give two specific cases showing how co-development/co-architecting in SiP impacts product definition, helps reducing silicon and package cost, and enhances features and performance.

Chip-package-board pathway design flows
Tom Whipple, Product Engineering Architect, Cadence

Today’s IC design process can no longer be done in a vacuum ignoring the realities of the package and PCB implementation. Package ball maps are typically created in a spreadsheet and PCB and IC pinout and component breakout are done without a view for how the pieces will fit together. The parts are brought together in a BGA and an attempt to resolve the many net crossings is made in the package layout tool. This is a tedious and error-prone process for even a single die package. This problem is exacerbated by shrinking feature size and increasingly difficult design, timing and power constraints that significantly reduce design margins. System on Chip designs are yielding to System in Package designs due to difficulties in scaling to advanced technology nodes. Designers require a hierarchical environment that enables a system-level exploration of topological solutions of the components in the design followed by pathway exploration. This should include the component routing breakouts on all substrates, and the optimal pin assignment to package, interposer and die components in the context of the whole system. Results from the pathway exploration must drive directly into physical implementation tools for physical layout and analysis.

Organic Interposer Technology and Embedded Passive/Active PCB
Tomoyuki Yamada, Sr. Field Applications Engineer, Organic Products, Kyocera America

This presentation consists of the development of a low CTE organic package for 2.5D interposer and the embedded passive/active PCB technologies. The new material set, identified as advanced organic package, combines low CTE core and build-up Dielectric materials to achieve a composite laminate CTE of 9-12 ppm / oC, which is positioned in between the device silicon and conventional board CTE. The technology roadmap of organic interposer technology including fine pitch flip chip, line and space etc. will be discussed. On embedded active/passive package, technical capabilities and challenges are discussed.

Wrap-Up Panel Discussion -- The Great Consolidation

The big Silicon Valley story of 2015, one that gained strength and momentum as the year progressed, is consolidation.  Be it on the device maker-side, the OSAT-side, the capital equipment supplier-side, or the end customer-side, consolidation has its benefits, primarily in achieving ever greater business efficiencies, but consolidation also has its costs, hidden or otherwise.  The panelists in Session 8 will discuss, with active audience participation, the merits and drawbacks of the consolidation spree as they see it, and will consider how consolidation will affect our industry’s ability to embrace the challenges presented by the new era of mobile miniaturization.